Dec. 16 / 17 / 18 / 19

Dec. 16

Time	Room	Session	Title	Lecturers
9:45 am – 12 pm	701	Tutorial 1	Talk on 3D Testing or Silicone Life Cycle Management. (Tentative)	Yervant Zorian (Chief Architect and fellow at Synopsys)
1:30 pm – 3:40 pm	701	Tutorial 2	Enhancing Trustworthiness in the Global IC Supply Chain	Giorgio Di Natale (Director of Research (CNRS) – TIMA Director, Université Grenoble-Alpes)
3:45 pm – 4:45 pm	701	Tutorial 3	Test Space Optimization techniques	Shamitha Rao (Sr. Manager Hardware Analytics and Test, Solutions Engineering, Synopsys India)

Dec. 17

Time	Room	Session	Title	Speakers
9 am – 9:40 am	101	Opening
9:40 am – 10:30 am	101	Keynote	New Design for Test Technologies for the Angstrom Era Multi-Die Designs	Janusz Rajski (Siemens EDA)
10:30 am – 11:20 am	101	Invited	3DIC and advanced packaging technologies for enabling the evolution of AI	Ryutaro Yasuhara (TSMC Japan 3DIC R&D Center)

Session 1 (ATS)

Time	Room	Paper ID	Title	Authors
1 pm – 1:25 pm	101	29	A Don’t Care Filling Method for Control Signals on State Transitions of Controllers to Minimize the Estimated Number of Test Patterns for Data-Paths	Haruta Tokuta, Toshinori Hosokawa (Nihon University), Masayoshi Yoshimura (Kyoto Sangyo University), Masayuki Arai (Nihon University)
1:25 pm – 1:50 pm	101	124	Weight-Aware Scan Chain Stitching for Shift Power Minimization under Routing Constraints	Rohit Badjatya, Kapil Sharma (Indian Institute of Technology Bombay), Makoto Ikeda, Masahiro Fujita (University of Tokyo), Virendra Singh (Indian Institute of Technology Bombay)
1:50 pm – 2:15 pm	101	104	Automatic Cell-Aware Software-Based Self-Test Generation for a RISC-V Core Local Interrupt Controller	Tobias Faller, Bernd Becker (University of Freiburg)
2:15 pm – 2:40 pm	101	86	Application-Aware Early-Exit Fault Classification for Video Decoder Using Miter-Based Analysis	Jun-Tsung Wu (Department of Electrical Engineering, National Sun Yat-sen University), Tong-Yu Hsieh (National San Yat-san University)

ATS Doctoral Thesis Award Contest

Time	Room	Title	Contestants
1 pm – 2:45 pm	701	TBA	TBA

Session 2 (ITC-Asia)

Time	Room	Paper ID	Title	Authors
1 pm – 1:25 pm	702	22	Descriptive Language For 3D IC Die-to-Die Interconnect Repair For IEEE P3405 Standard	Ashish Reddy Bommana, Anshuman Chandra, Moiz Khan (Siemens EDA)
1:25 pm – 1:50 pm	702	39	A High-Precision Pre-Bond TSV Delay-Fault Detection Technique Using Digitally Controlled Delay Lines	Zhongyuan Liang (School of Microelectronics Hefei University of Technology), Huaguo Liang (Hefei University of Technology), Weikun Chen (School of Computer and Information Hefei University of Technology), Xianrui Dou (School of Microelectronics Hefei University of Technology)
1:50 pm – 2:15 pm	702	15	A mm-Wave Frontend Circuit with High Accuracy Power Levels for ATE to Test 76- to 81- GHz Radar IC	Norio Kobayashi (Advantest Corporation), Minoru Iida, Masayuki Nakamura, Hideki Shirasu (ADVANTEST CORPORATION)
2:15 pm – 2:40 pm	702	91	A Kelvin Connection-Based Approach Using an Internal DFT Technique To Compensate Resistance Variability In Semiconductor Testing	Rinika Paul (ATE Test Engineer, Infineon Technologies, India)

Session 3 (ATS)

Time	Room	Paper ID	Title	Authors
3 pm – 3:25 pm	101	34	AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging	Hongqin Lyu, Yonghao Wang (Institute of Computing Technology, Chinese Academy of Sciences), Yunlin Du (University of Newcastle), Mingyu Shi (NANJING UNIVERSITY SCHOOL OF INTEGRATED CIRCUITS), Zhiteng Chao, Wenxing Li, Tiancheng Wang, Huawei Li (Institute of Computing Technology, Chinese Academy of Sciences)
3:25 pm – 3:50 pm	101	68	Exploring the Limits of LLMs for System-Level Test Program Generation: Can LLaMas Outrun Darwin?	Denis Schwachhofer, Steffen Becker (University of Stuttgart), Stefan Wagner (Technical University of Munich), Matthias Sauer (Advantest Europe GmbH), Ilia Polian (University of Stuttgart)
3:50 pm – 4:15 pm	101	52	Transformer-Based Architecture for Fault Propagation Modeling in Transient Fault Analysis	Chia-Ying Lin (Dept. Electrical Engineering, National Tsing Hua University), Jing-Jia Liou (Dept. Electrical Engineering/National Tsing Hua University), Harry H. Chen (MediaTek Inc.)
4:15 pm – 4:40 pm	101	42	Testing of Passive Memristive Crossbars in AI Hardware Accelerators	Shanmukha Mangadahalli Siddaramu (karlsruhe institute of technology), Mahta Mayahinia, Surendra Hemaram (Karlsruhe Institute of Technology (KIT)), Sule Ozev (Arizona State University), Mehdi Tahoori (Karlsruhe Institute of Technology)

Session 4 (ATS)

Time	Room	Paper ID	Title	Authors
3 pm – 3:25 pm	701	14	The Low-Latency UCIe-Compliant Spiral Layouts of TSV Arrays Against the Clustered Faults	Bowen Tan, Xiaole Cui, Zhaohong Lin (Peking University Shenzhen Graduate School)
3:25 pm – 3:50 pm	701	26	LLM-Design Platform for Thermal-Failure-Aware 3D Chiplet Layout via Iterative Parameter Analysis	Tai Song (Anhui University), Senling Wang (Dept. of Computer Science, Faculty of Engineering, Ehime University), Xiaoqing Wen (Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology)
3:50 pm – 4:15 pm	701	61	Software-Defined Secure Island for Testing Chiplet Systems	Hisashi Okamoto (Ehime University), Senling Wang (Dept. of Computer Science, Faculty of Engineering, Ehime University), Hiroshi Kai, Hiroshi Takahashi, Yoshinobu Higami (Ehime University), Hiroyuki Yotsuyanagi (Tokushima University), Tianming Ni (Anhui Polytechnic University), Tai Song (Anhui University), Xiaoqing Wen (Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology)
4:15 pm – 4:40 pm	701	99	Fault-Aware Repair Scheme for Inter-Die Interconnects of Chiplet-Based Chips	Yi-Chun Huang, Jin Fu Li, Hong-Siang Fu (National Central University), Yung-Ping Lee (Industrial Technology Research Institute)
4:40 pm – 5:05 pm	701	131	Chiplet Interconnect Repair for Clustered Defects with Minimal Propagation Delay	Po-Yao Chuang, Erik Jan Marinissen (imec)

Session 5 (ITC-Asia)

Time	Room	Paper ID	Title	Authors
3 pm – 3:25 pm	702	92	Monitor-Like Efficiency with Detector-Level Accuracy: Frontier-Aligned Timing Monitor for AI Accelerators	Wei-Ji Chao, Tsung-Chun Chen (Department of Electrical Engineering, National Sun Yat-sen University), Chu-Cheng Chen (Institute of Integrated Circuit Design, National Sun Yat-sen University), Tong-Yu Hsieh (National San Yat-san University)
3:25 pm – 3:50 pm	702	98	A Fast Nonlinear Trimming Method Driven by Performance Deviation	Yangxinzi Zhou, Wenfa Zhan, Jiangyun Zheng, Xueyuan Cai, Shiyu Zhao (Anqing Normal University)
3:50 pm – 4:15 pm	702	114	Automatic IR-Informed Timing and Timing-Aware IR Optimization	Po-Chieh Yen, Wei-Shen Wang, Shao-Yu Wu, Bing-Chen Li, James Chien-Mo Li (National Taiwan University), Norman Chang, Ying-Shiun Li, Lang Lin, Akhilesh Kumar (Ansys Inc.)

Dec. 18

Time	Room	Session	Title	Speakers
9 am – 9:50 am	701+702	Keynote	Software-Based Self-Test with Formal Methods for RISC-V Ecosystems	Bernd Becker (University of Freiburg)
9:50 am – 10:40 am	701+702	Invited	Next-Generation SoC Design “Chiplet 2.5D/3D Technology” and Beyond	Kazuyuki Irie (GUC Japan)

Session 6 (ITC-Asia)

Time	Room	Paper ID	Title	Authors
11 am – 11:25 am	701+702	3	FALCO-WAFER : Feature-Aware Lightweight Contextual Detector for Wafer Defect Detection	Haotian Zhang, Shurong Cao, Ningmu Zou (School of Integrated Circuits, Nanjing University, Suzhou, China.)
11:25 am – 11:50 am	701+702	11	Design for Testability for VLSI Circuits with A Large Number of Unknown Test Response Sources	Dong Xiang, Wenfei Wang (Tsinghua University)
11:50 am – 12:15 pm	701+702	54	Fault-Detecting Randomized Benchmarking for Testing Quantum Processors	Cynthia Kuan, Cheng-Yun Hsieh, Shan-Chi Shih, James Chien-Mo Li (National Taiwan University)
12:15 pm – 12:40 pm	701+702	67	Collide & Conquer: Side-channel Attack on Hyper-dimensional Computing (HDC) Accelerators	Brojogopal Sapui (Kalrsurhe Institute of Technology, Germany), Mahboobe Sadeghipour Roudsari, Mehdi Tahoori (Karlsruhe Institute of Technology)

Session 7 (ATS)

Time	Room	Paper ID	Title	Authors
11 am – 11:25 am	802	17	Multi-Agent Reinforcement Learning for Performance Calibration and Optimization of Integrated mmW Power Amplifiers	Valentin Coppola, Florent Cilici, Sylvain Bourdel, Estelle Lauga-Larroze, Salvador Mir, Florence Podevin, Manuel Barragan (TIMA)
11:25 am – 11:50 am	802	24	Ultra-Fine Frequency Offset Synthesis Technique Based on Cascaded Phase Interpolators	Cao Wang (Shanghai Jiao Tong University), Shengbo Liu, Yindong Xiao (University of Electronics Science and Technology of China), Xiaochun Li (Shanghai Jiao Tong University), David Keezer (Eastern Institute of Technology, Ningbo)
11:50 am – 12:15 pm	802	79	TDR-Based S-Parameter Estimation of Signal Path to DUT Utilizing Built-In Driver and Comparator of ATE	Kazuki Shirahata, Masahiro Ishida (ADVANTEST Corp.), Koji Asami, Toru Nakura, Akio Higo, Tetsuya Iizuka (The University of Tokyo)
12:15 pm – 12:40 pm	802	80	Advanced Strategies for Uncertainty‑Guided Live Measurement Sequencing in Fast, Robust SAR ADC Linearity Testing	Thorben Schey (University of Stuttgart), Khaled Karoonlatifi (Advantest Europe GmbH), Michael Weyrich, Andrey Morozov (University of Stuttgart)

Special Session

Time	Room	Title	Organizer
1:40 pm – 3:10 pm	701+702	6 Years of Graduate School Intelligent Methods Test and Reliability	Ilia Polian

Session 8 (ITC-Asia)

Time	Room	Paper ID	Title	Authors
1:30 pm – 1:55 pm	802	56	Improving Effect-Cause Diagnosis Performance with Minimal Memory Overhead on Asymmetric Partition Trees (APT)	Wu-Tung Cheng, Szczepan Urban, Manish Sharma, Jakub Janicki (Siemens EDA)
1:55 pm – 2:20 pm	802	55	Exploiting weak detections for optimizing pattern generation in Defect-Oriented Cell-Aware ATPG	Alessandro Ciullo, Stephan Eggersglüß, Daniel Tille, Andreas Glowatz (Siemens EDA), Giusy Iaria, Paolo Bernardi (Politecnico di Torino)
2:20 pm – 2:45 pm	802	58	Improving ATPG through Abort-Driven Dynamic Learning (ADDLe)	Peter Wohl, John Waicukauski, Jonathon Colburn, Yasunari Kanzawa (Synopsys)
2:45 pm – 3:10 pm	802	76	Test Point Insertion for an Approximate Multiplier Using Enhanced Static Segment Method to Reduce Test Patterns and Overdetection	Takuya Kishimoto, Hiroyuki Yotsuyanagi (Tokushima University)

Industry Session

Time	Room	Title	Authors
3:25 pm – TBA	701+702	TBA	TBA

Session 9 (ATS)

Time	Room	Paper ID	Title	Authors
3:25 pm – 3:50 pm	802	20	Radiation-Resistant ZnO Thin-Film Transistor Voltage Reference	Na Bai, Ge Guocheng (Anhui University), Aibin Yan (Hefei University of Technology), Xiaoqing Wen (Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology)
3:50 pm – 4:15 pm	802	60	Veritas-PUF: A Countermeasure against X-Ray Tampering and Side Channel Attacks	Nasr-Eddine Ouldei Tebina (TIMA/Fortaegis Technologies), Luc Salvo (SIMAP/Grenoble INP), Marc Xander Makkes (Fortaegis Technologies), Nacer-Eddine Zergainoh (TIMA), Paolo Maistri (TIMA/CNRS)
4:15 pm – 4:40 pm	802	93	Improving RO-PUFs on FPGAs: A Filtering Approach for Improved Reliability and Entropy	Vasilii Kulagin, Giorgio Di Natale (TIMA), Elena-Ioana Vatajelu (TIMA, CNRS)
4:40 pm – 5:05 pm	802	108	EMBER: A Cycle-based Framework for Early-Stage Reliability Assessment in Parametric RTL Designs	Alessandro Veronesi, Leticia Maria Bolzani Pöhls (IHP-microelectronics), Michele Favalli (University of Ferrara), Milos Krstic (IHP-microelectronics), Davide Bertozzi (University of Manchester)

Dec. 19

Session 10 (ATS)

Time	Room	Paper ID	Title	Authors
9 am – 9:25 am	701	7	Dynamic Step-Size Single-Write Pattern Trimming for STT-MRAM Reference Resistance Optimization	Chenxi Liu (Zhejiang University), Yaxing Zhou (Zhejiang Hikstor Technology Co., Ltd.), Pingyang Huang (Zhejiang University), Shikun He (Zhejiang Hikstor Technology Co., Ltd.), Zhiyuan Cheng (Zhejiang University)
9:25 am – 9:50 am	701	77	Two-Step Transition Zeroization Techniques for MLC STT-MRAM	Shyue-Kung Lu (National Taiwan University of Science and Technology), Kohei Miyase (Kyushu Institute of Technology)
9:50 am – 10:15 am	701	85	Streamlining MBIST Footprint : A Strategic Approach through Memory Centric Clustering and Controller Placement	Manya Gupta, Somya Gupta, Arshad Qureshi, Vishal Diwan (Texas Instruments)
10:15 am – 10:40 am	701	118	March-CIM: A MBIST-guided Modified March Test for SRAM-based Computation-in-Memory	Sina Bakhtavari Mamaghani (karlsruhe Institute of Technology), Jongsin Yun, Martin Keim (Siemens EDA), Mehdi Tahoori (Karlsruhe Institute of Technology)

Session 11 (ITC-Asia)

Time	Room	Paper ID	Title	Authors
9 am – 9:25 am	702	9	A Speed Learning Scheme To Mitigate The Silent Data Corruption in a Multi-Core Design	Yun-Chieh Wang, Chun-Teng Chao (NTHU), Shi-Yu Huang (NTHU, STPI/NIAR), Robert Chen (Taiwan Electronic System Design Automation)
9:25 am – 9:50 am	702	97	Fault injection and Tolerance Analysis of Battery Management Systems Using SystemC-AMS	Hao-Yang Chi, Jing-Jia Liou (Dept. Electrical Engineering/National Tsing Hua University), Harry Chen (MediaTek)
9:50 am – 10:15 am	702	112	Analysis and Improvement of Parallel Implementation of Linear FSMs for High-Speed Stochastic Computing	Hideyuki Ichihara, Kota Okahara, Tomoo Inoue (Hiroshima City University)
10:15 am – 10:40 am	702	127	Adaptive Fault Resilience for Early-Exit DNNs	Rama Mounika Kodamanchili, Natalia Cherezova (Tallinn University of Technology), Mahdi Taheri (Brandenburg Technical University, Cottbus, Germany), Maksim Jenihhin (Tallinn University of Technology)

ETT workshop

Time	Room	Title	Authors
am (TBA)	802	TBA	TBA

Session 12 (ATS)

Time	Room	Paper ID	Title	Authors
10:55 am – 11:20 am	701	90	How Long Can They Learn? A Methodology to Assess Endurance in Analog Memristive Synapses during On-line Training	Alexandra Koroleva (TIMA Laboratory), Salah Daddinounou (TIMA – INPG), Monica Burriel (LMGP – CNRS), Elena Ioana Vatajelu (TIMA – CNRS)
11:20 am – 11:45 am	701	105	Reliability Assessment of Early Exit Deep Convolutional Neural Networks	Georgios Konstantinidis, Maria K. Michael, Theocharis Theocharides (University of Cyprus and KIOS Research and Innovation Center of Excellence)
11:45 am – 12:10 pm	701	109	Breaking the One-Shot Barrier: Progressive Error Detection in FSM via Key-Driven Corruption	Leon Li, Alex Orailoglu (University of California, San Diego)
12:10 pm – 12:35 pm	701	122	Fault-Tolerant and Low-Latency Stochastic Neural Networks via Adaptive Bitstream Precision	Roshwin Sengupta (University of Stuttgart), John P. Hayes (University of Michigan), Ilia Polian (University of Stuttgart)

AI-TREATS workshop

Time	Room	Title	Authors
pm (TBA)	802	TBA	TBA