Keynote 1 (Wednesday, Dec. 17)

Title: New Design for Test Technologies for the Angstrom Era Multi-Die Designs

Speaker: Janusz Rajski (Siemens EDA)

Abstract

AI/ML computing, hyperscale data centers, networking, mobile, and automotive are pushing adoption of new technology nodes to satisfy growing demand for computing power. The combined effect of heterogeneous integration and the sub-20 Angstrom process results in design complexities presenting fundamental reliability challenges. The reliable operation of these complex systems throughout the entire long lifecycle is the greatest challenge facing the semiconductor industry today.

In this keynote, we will ask some of the most fundamental questions: How can we further improve the effectiveness of manufacturing screening and reduce test escapes, especially the silent data corruption errors reported by many companies? Can high-voltage stress test replace burn-in to reduce early life failures? Can a deterministic structural test, applied periodically during in-system operation, achieve the required high reliability? How can preventive maintenance use environmental monitoring to detect load conditions or silicon aging and prevent the system malfunction? What new DFT architectures are needed to handle designs with hundreds of cores, facilitate bring up and debug? How can these problems be solved with cost/time constraints? The DFT/SLM flow has become complex; how and where can AI/ML help with productivity and quality of results?

About the Speaker

During his tenure at Mentor Graphics and Siemens, Janusz has built a strong R&D organization with a focus on innovative DFT and SLM technologies. The team has developed several revolutionary products: TestKompress, Cell-Aware Test, and Streaming Scan Network. He has published more than 280 IEEE research papers and is a co-inventor of 130 US and international patents. A Lifetime Fellow of the IEEE, he holds a Ph.D. degree in electrical engineering as well as an honorary doctorate from the Poznań University of Technology. In 2003, he was awarded the prestigious title of “Professor of Science” by the President of Poland. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor’s DFT business to its current position as the #1 test business in EDA”. In 2018, Janusz received the Siemens Inventor of the Year Lifetime Achievement Award “in recognition of his outstanding achievements which have led to valuable inventions in the field of DFT of integrated circuits”. In 2022 he received the Siemens Inventor of the Year Award for co-inventing the Streaming Scan Network.

Keynote 2 (Thursday, Dec. 18)

Title: Software-Based Self-Test with Formal Methods for RISC-V Ecosystemsds – SBST – RISC-V

Speaker: Bernd Becker (University of Freiburg)

Abstract

The growing number of embedded systems and their ever-increasing diversity represents a major challenge for the technology industry. Requirements like energy efficiency, reliability, security, safety and high computational capability for edge devices spawned the need for customized System-On-a-Chips (SoC) with short time to market (TTM) windows and low production costs. The RISC-V Instruction Set Architecture (ISA) targets this market by providing a free and open ISA developed and extended by the open-source community as well as many companies.

A commercially successful development of edge devices for a wide range of applications requires an entire ecosystem of tools and hardware components. Ensuring the safe, secure, and reliable design and operation of these devices is an indispensable, but challenging requirement for many of these applications. Among others, the Scale4Edge project aims to address this challenge by developing a comprehensive RISC-V-based ecosystem, that, on the one hand, allows the automated creation of whole processor families that provide ISA extensions depending on the targeted use-case and, on the other hand, ensures the correct functioning throughout the whole design process and lifetime of an edge system.

In our presentation we focus on a test strategy to find manufacturing defects introduced during production, and moreover, to detect degradation after production which is necessary to guarantee quality and reliability of a RISC-V ecosystem. In particular, we discuss the potential of Software-Based Self-Test (SBST) in this context.

SBST is a well-known concept that allows for at-speed testing of processors and on-chip devices via the processor itself. In form of Self-Test Libraries (STLs) SBST is in use by many core and semiconductor companies which provide STLs together with their devices for safety-critical applications. Even though SBST might bring many benefits, its creation often is time-consuming and costly, requiring significant manual labor of a skilled developer that knows about the intricacies of the processor’s micro-architecture at hand and also takes the test conditions into account.

A promising way to at least mitigate this problem is to use formal methods based on Bounded Model Checking (BMC) with underlying sophisticated, state-of-the-art SAT solvers. BMC has been shown to allow semi-automatic generation of SBSTs using a so-called Validity Checker Module (VCM) for specifying additional constraints. However, the specification of SBST constraints for entire processor families, as they exist in a RISC-V-based ecosystem, poses an additional challenge. We demonstrate how an extension of the VCM concept can be used to target multiple RISC-V processor cores in a semi-automated way. Furthermore, additional extensions are discussed: How can the fault model used for SBST generation be adapted to the needs of nanoelectronics circuitry? Which environmental conditions can be considered? To which extent is it possible to also use SBST for other on-chip circuitry?

Taken together, we aim for SBST which explores the limit of a formal methods-based approach and in this sense bridges the gap between structural and system-level tests.

About the Speaker

Bernd Becker received the Diploma and Ph.D. degree in mathematics and computer science from the University of Saarland in Saarbrücken, Germany, in 1979 and 1982, respectively. From 1989-1995, he was an Associate Professor for Complexity Theory and Efficient Algorithms at the J.W. Goethe University Frankfurt. Since 1995, he has been a professor at the University of Freiburg and was head of the Chair of Computer Architecture at the Faculty of Engineering until his retirement in 2021.

He has published more than 500 scientific papers and supervised more than 30 PhD students who now hold leading positions in industry and universities as well. His research activities are mainly in the field of computer-aided design, test and verification of (digital) circuits and systems. More recently, he has worked on the verification of security issues for embedded systems and on test techniques for nanoelectronic circuits. He has acquired numerous third-party funded projects and was co-spokesperson of the Transregional Collaborative Research Center “Automatic Verification of Complex Systems (AVACS)” from 2003 to 2015. In 2021, Bernd Becker received the EDA Medal for lifetime achievements in research, development, promotion and application in the field of Electronic Design Automation (EDA) by edacentrum Germany, he is a Fellow of IEEE and a member of Academia Europaea.