Invited Talk 1 (Wednesday, Dec. 17)
Title: 3DIC and advanced packaging technologies for enabling the evolution of AI
Speaker: Ryutaro Yasuhara (TSMC Japan 3DIC R&D Center)
Chair: TBA
Abstract
With the evolution and increasing demand of AI, 3DIC and advanced packaging technologies are becoming essential keys for the growth of semiconductor industry. TSMC Japan 3DIC R&D Center, as the R&D hub of advanced packaging technologies in Japan, creates new technologies for enabling the evolution of AI. In this talk, the perspective and progress of TSMC’s 3DIC and advanced packaging technologies will be discussed.
About the Speaker
After receiving Ph.D degree from the University of Tokyo, Ryutaro Yasuhara joined Panasonic Corporation in 2011 and engaged in the device and process development of nonvolatile memories. During the period, he experienced leading national R&D projects and being assignee in imec, Belgium. He joined TSMC in 2021, engaging in the development of advanced packaging technologies.
Invited Talk 2 (Thursday, Dec. 18)
Title: Next-Generation SoC Design “Chiplet 2.5D/3D Technology” and Beyond
Speaker: Kazuyuki Irie (TSMC Group, GUC Japan)
Chair: TBD
Abstract
Demand is growing globally in the fields of AI, HPC, AR/VR and ADAS systems, especially ultra-high-speed, ultra-large-scale design, and multi-function circuits with HBM. For those applications, needs advanced node processes, and it is related to serious challenges, such as increased difficulty level in the circuit design with manufacturing rules and functional expansion, as well as longer development schedules and higher costs. Chiplet 2.5D/3D technologies has emerged as a solution, and GUC as ASIC design service company in TSMC Group, is one of the industry leaders in this cutting-edge technology. At this session, I will introduce the latest Chiplet technology, design techniques used in actual Chiplet products, and more next cutting-edge technologies.
About the Speaker
Mr. Irie is currently a Fellow of GUC President Office and leading GUC-Japan design team for project engagements and developments. He has 20+ years of chip design experiences and specialized in ultra low power, high-performance hyper-scale ASIC design for HPC, AI and networking applications. He also has abundant experience in advanced process technology like N7, N6, N5. N3 and N2 as well as 2.5D/3D advanced package technologies.