Title: Silicon Lifecycle Management: From Design to In-Field Reliability
Speaker: Wu Yang (Siemens EDA)
Abstract
Effective silicon lifecycle management is essential, encompassing design, new product introduction, volume production, in-field operation, and customer return analysis. The design phase mandates Design-for-Test (DFT) insertion, utilizes defect-oriented fault modeling for optimal test quality, and leverages embedded IPs for in-life monitoring. Throughout silicon learning, from bring-up to rapid yield ramp-up and customer return analysis, scan diagnosis and diagnosis-driven yield analysis play a pivotal role. Finally, the in-field stage ensures safety, security, and reliability through FuSa, hardware security, in-system testing for mission-critical applications, and embedded analytics for functional monitoring and remote debug.
Title: Synopsys Scalable E2E Test Solution with AI Driven Optimization
Authors: Yuya Suzuki, Shamitha Rao, and Sri Ganta
Speaker: Sri Ganta (Synopsys)
Abstract
Modern AI and HPC chips present significant test challenges due to their size, complexity, and presence of hundreds to thousands of IP cores ? both identical and non-identical cores with abutted tile-based floorplan requirements. Advanced technology nodes used in these chips introduce new failure modes, which require additional pattern to target advanced fault models like slack-based faults, cell-aware faults ? which increase the test time and the test data volume (TDV), hence the test costs. Also often, these devices require testing to be done beyond manufacturing and in In-system and In-field applications also.
Synopsys TestMAX test solution addresses all these challenges. Synopsys SEQ is a PRPG based sequential compression/decompression logic that is scalable to designs of any sizes, its unified architecture allows it to be used as Logic BIST also for Burn-in and In-system test applications, and it offers significantly less TDV. Synopsys Streaming Fabric (SF) is a high-speed test fabric that delivers scan data to each core, better suits for tile-based abutted floor plans, and it optimizes the bandwidth for both identical and non-identical cores. Synopsys SLM IP, HSAT (High-Speed Access Test) allows same test patterns to be ported on to functional high-speed IOs like PCIe or USB interfaces for In-system and In-field tests. In addition, this session introduces Synopsys TSO.ai, an AI driven test space optimization product, which optimizes DFT configuration as well as ATPG parameters to reduce the pattern count, which reduces test time, hence the test costs.
Title: Case Studies of Test Solutions in 3D-IC and Efforts to Reduce Test Time
Speaker: Shuji Hamada (Socionext)
Abstract
Advanced 3D integration technologies enable significant footprint reduction and performance gains through die stacking. However, they also introduce complex design and testability challenges. Key DFT issues include limited probe access to stacked dies and inter-die testing, addressed by the IEEE Std 1838.
This presentation outlines the application of EDA’s 3D test solutions compliant with the standard, and strategies to manage increased test time due to high-density 3D-ICs. Synopsys’ HSAT(High-Speed Test & Access) IP supports high-speed scan testing via PCIe, but it requires system-level techniques to maintain PCIe operation during test. Socionext, leveraging its “Solution SoC” business model, covers the full development flow from design to test, and has addressed these challenges through close collaboration between its system and test engineering teams.
Keywords: 3D, IEEE std. 1838, PCIe, HSAT, scan test
Title: Beyond AI: Securing the Future of IC Design
Speaker: Marc X. Makkes (Fortaegis Technologies)
Abstract
Artificial Intelligence is rapidly reshaping IC design, promising unprecedented automation and accelerated time-to-market. But this transformative capability comes with a less examined cost: a dramatically expanded attack surface and a new class of sophisticated vulnerabilities emerging at a speed and scale the industry is not prepared for. While much of the industry focuses on what AI can optimize, we have not fully confronted what it exposes.
This talk argues that the increasing complexity of modern ICs – amplified by AI Integration – is creating a “perfect storm” for security breaches. Traditional post-fabrication detection methods are quickly becoming insufficient against adaptive, AI-driven threats. We will explore how AI can be leveraged by malicious actors, and why a paradigm shift is crucial – moving from reactive detection to fundamentally secure IC design.
Join this session to understand the emerging security landscape, identify the critical vulnerabilities introduced by AI-driven IC development, and discuss the proactive design methodologies needed to build resilient and secure Hardware systems for the coming decade. This isn’t just about adding another layer of security; it’s about redefining how we architect trust at the silicon level.