Technical Program

At-a-Glance of Regular & Industry Sessions

September 4, Wednesday

Location Room 1206 Room 1205 Room 1204
1:00 pm

5:45 pm
1A: Analog and Mixed-Signal Test  1B: ATE Design  1C: Special Session 1   
2A: Hardware Oriented Security 2B: Design for Testability  2C: Embedded Tutorial 
3A: Hotspot Analysis / Yield Analysis 3B: ATPG  3C: Special Session 2 (ITC-India Excellent Papers) 
September 5, Thursday
1:00 pm

5:20 pm
4A: Trust and Safety  4B: 3D IC Test / SRAM BIST   4C: Industry Session 1 & Special Session 3 
5A: Fault Tolerance  5B: Delay Test  5C: Industry Session 2 

Regular&Industry Sessions

Sept.4 Wednesday 1:00 pm – 2:15 pm

Session 1A: Analog and Mixed-Signal Test, @1206 room

Chair: Hans Kerkhoff (University of Twente)

1A-1 Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in μV-order by DC-AC Conversion
♠Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang (Gunma University), Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa (ROHM Semiconductor), Anna Kuwana, Kazumi Hatayama and Haruo Kobayashi (Gunma University)

1A-2 Crest Factor Controlled Multi-Tone Signals for Analog/Mixed-Signal IC Testing
♠Yukiko Shibasaki (Gunma University), Koji Asami (ADVANTEST CORPORATION), Anna Kuwana, Kosuke Machida, Yuanyang Du, Akemi Hatta (Gunma University), Kazuyoshi Kubo (Oyama National College of Technology) and Haruo Kobayashi (Gunma University)

1A-3 A Selection Method of Ring Oscillators for An On-chip Digital Temperature And Voltage Sensor
♠Yousuke Miyake, Yasuo Sato and Seiji Kajihara (Kyushu Institute of Technology)


Session 1B: ATE Design @1205 room

Chair: Xinli Gu (Huawei)

1B-1 Test-Plan Optimization for Flying-Probes In-Circuit Testers
♠Luciano Bonaria, Maurizio Raganato (SPEA), Giovanni Squillero and Matteo Sonza Reorda (Politecnico di Torino)

1B-2 An FPGA-Based Data Receiver for Digital IC Testing
♠Wei-Chen Huang, Guan-Hao Hou, Jiun-Lang Huang (National Taiwan University) and Terry Kuo (Open ATE)

1B-3 Did We Test Enough? Functional Coverage for Post-Silicon Validation
♠Sebastian Pointner and Robert Wille (Johannes Kepler University Linz)

Session 1C: Special Session 1, @1204 room

Chair: Xiaoqing Wen (Kyushu Institute of Technology)

1C-1 The New High-Bandwidth Test Access Paradigm
♠ Robert Ruiz (Synopsys, Inc.) *Speaker is changed

1C-2 Test Challenges and Solutions for AI, SoC DFT Architecture and Next Level of Quality
♠Wu Yang (Mentor, a Siemens Business)

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Sept.4 Wednesday 2:45 pm – 4:00 pm

Session 2A:  Hardware Oriented Security, @1206 room

Chair: Jiun-Lang Huang (National Taiwan University)

2A-1 Implementation of Parametric Hardware Trojan in FPGA
♠Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li and Yu Hu (Chinese Academy of Sciences)

2A-2 Time-Related Hardware Trojan Attacks on Processor Cores
♠Man-Hsuan Kuo, Chun-Ming Hu and Kuen-Jong Lee (National Cheng Kung University)

2A-3 Instruction Vulnerability Test and Code Optimization against DVFS attack
♠Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li and Zhimin Zhang (Chinese Academy of Sciences)

Session 2B: Design for Testability, @1205 room

Chair: Tong-Yu Hsieh (National Sun Yat-sen University)

2B-1 An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis
♠Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara and Tomoo Inoue (Hiroshima City University)

2B-2 A Case Study of Testing Strategy for AI SoC
♠Haiying Ma, Rui Guo, Quan Jing, Jing Han (Enflame Technology Corporation), Yu Huang, Rahul Singhal, Wu Yang, Xin Wen and Fanjin Meng (Mentor, a Siemens Business )

2B-3 Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques
♠Stephan Eggersglüß (Mentor, a Siemens Business)

Session 2C: Embedded Tutorial, @1204 room

Chair: Shi-Yu Huang (National Tsing Hua University)

Recent Advances in Capacitive Non-Contact Measurements of Physiological and Behavioral Signals

Akinori Ueno (Tokyo Denki University)

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Sept.4 Wednesday 4:30 pm – 5:45 pm

Session 3A: Hotspot Analysis / Yield Analysis, @1206 room

Chair: Krishnendu Chakrabarty (Duke University)

3A-1 A Static Method for Analyzing Hotspot Distribution on the LSI
♠Kohei Miyase, Yudai Kawano (Kyushu Institute of Technology), Shyue-Kung Lu (National Taiwan University of Science and Technology), Xiaoqing Wen and Seiji Kajihara (Kyushu Institute of Technology)

3A-2 Wafer Plot Classification Using Neural Networks and Tensor Methods
♠Ahmed Wahba, Chuanhe Shan, Li-C. Wang (UC Santa Barbara) and Nik Sumikawa (NXP Semiconductors)

Session 3B: ATPG, @1205 room

Chair: Ying Wang (Chinese Academy of Sciences)

3B-1 Race and Glitch Handling: A Test Perspective 
♠Kun-Han Tsai (Mentor, a Siemens Business)

3B-2 Optimization of Cell-Aware ATPG Results by Manipulating Library Cells’ Defect Detection Matrices
♠Zhan Gao, Min-Chun Hu, Jos Swenton, Santosh Malagi, Jos Huisken, Kees Goossens and Erik Jan Marinissen (IMEC, Cadence Deign Systems, Eindhoven University of Technology, National Tsing Hua University)

3B-3 Characterization of Locked Sequential Circuits via ATPG
♠Danielle Duvalsaint, Zeye Liu (Carnegie Mellon University), Ananya Ravikumar (PES University) and Ronald D. Blanton (Carnegie Mellon University)

Session 3C:  Special Session 2 (ITC-India Excellent Papers), @1204 room

Chair: Rahul Singhal (Mentor, a Siemens Business)

3C-1 Test Cost Reduction through increase in multi-site testing with reduced scan-out pins
♠Jaidev Shenoy, Kushal Kamal, Kelly Ockunzzi (GlobalFoundries), Virendra Singh (IIT Bombay)

3C-2 Improved Diagnosis Methodology for Multi-Defect Scenarios in High Compression Scan Based Designs
♠Bharath Nandakumar, Sameer Chillarige, Anil Malik, Atul Chhabra (Cadence Design Systems), Wilson Pradeep, Prakash Narayanan (Texas Instruments)

3C-3 Application of Test Techniques for Improving Silicon to Pre-Silicon Timing Correlation
♠Reecha Jajodia, Kevin Zhou, Jaison Kurien, Tezaswi Raja, Manikandan P, Karthik Joshi, Prashant Singh, Vinayak Srinath, Jonathan Colburn, Sarvesh Sharma (nVidia)   (3C-3 Canceled)

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Sept.5 Thursday 1:00 pm – 2:25 pm

Session 4A: Trust and Safety, @1206 room

Chair: Koji Asami (ADVANTEST CORPORATION)

4A-1 Low Cost Recycled FPGA Detection Using Virtual Probe Technique
♠Foisal Ahmed, Michihiro Shintani and Michiko Inoue (Nara Institute of Science and Technology)

4A-2 An On-chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips
♠Ahmed Ibrahim and Hans G. Kerkhoff (University of Twente)

4A-3 A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems
♠Sebastian Huhn (University of Bremen), Daniel Tille (Infineon Technologies AG) and Rolf Drechsler (University of Bremen)

Session 4B: 3D IC Test / SRAM BIST, @1205 room

Chair: Tsai Hans (Mentor, a Siemens Business)

4B-1 A Framework for TSV based 3D-IC to Analyze Aging and TSV Thermo-mechanical stress on Soft Errors
♠Raviteja P Reddy, Amit Acharyya (Indian Institute of Technology Hyderabad) and Saqib Khursheed (University of Liverpool)

4B-2 A Post-bond TSVs Test Solution for Leakage Fault
♠Yang Yu, Zhiming Yang and Kangkang Xu (Harbin Institute of Technology)

4B-3 A Novel BIST Algorithm for Low-voltage SRAM
♠Zhikuang Cai, Ying Wang, Shihuan Liu, Kai Lv and Zixuan Wang (Nanjing University of Posts and Telecommunications)

Session 4C: Industry Session 1 & Special Session 3, @1204 room

Chair: Toru Nakura (Fukuoka University)

4C-1 Overcoming Challenges for Wafer-Level Silicon Photonics Production and Wafer Acceptance Tests
♠Sia Choon Beng (FormFactor Inc.), Johnny Yap, Ashesh Sasidharan, Jun Hao Tan, Robin Chen, Jacobus Leo, Soon Leng Tan and Guo Chang Man (GlobalFoundries Singapore)

4C-2 Improved Design-to-Test Flow Achieves Faster Time-to-Market
♠Akira Hasegawa (Syswave Corp.)

4C-3 Special Talk: High Quality and Low Cost Test for Mixed Signal SOCs
♠Malav Shah (Texas Instruments, Inc)

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Sept.5 Thursday 4:05 pm – 5:20 pm

Session 5A: Fault Tolerance, @1206

Chair: Akio Higo (University of Tokyo)

5A-1 A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells
♠Zhiyuan Song, Aibin Yan, Jie Cui, Zhili Chen, Xuejun Li (Anhui University) and Xiaoqing Wen (Kyushu Institute of Technology), Chaoping Lai (Anhui University), Zhengfeng Huang, Huaguo Liang(Hefei University of Technology)

5A-2 A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection
♠Tong-Yu Hsieh, Kuang-Chun Lin and Hsin-Hsien Lin (National Sun Yat-sen University)

5A-3 Squeezing the Last MHz for CNN Acceleration on FPGAs
♠Li Li, Dawen Xu, Kouzi Xing (Hefei University of Technology), Cheng Liu, Ying Wang, Huawei Li and Xiaowei Li (Chinese Academy of Sciences)

Session 5B: Delay Test, @1205 room

Chair: Haruo Kobayashi (Gunma University)

5B-1 On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs
♠Yousuke Miyake, Seiji Kajihara (Kyushu Institute of Technology) and Poki Chen (National Taiwan University of Science and Technology)

5B-2 Online Testing of Clock Delay Faults in a Clock Network
♠Wei Chu and Shi-Yu Huang (National Tsing Hua University)

5B-3 On Delay Measurement under Delay Variations in Boundary Scan Circuit with Embedded TDC
♠Shuya Kikuchi, Hiroyuki Yotsuyanagi and Masaki Hashizume (Tokushima University)

Session 5C: Industry Session 2, @1204 room

Chair: Keno Sato (ROHM Semiconductor)

5C-1 Artificial Intelligence for Super Efficiency and Yield Improvement in Semiconductor Testing
♠Kosuke Ikeda (ADVANTEST CORPORATION)

5C-2 Test Scheduling Application of Hierarchical ATPG for Industrial Design
♠Hiroyuki Iwata (Renesas Electronics Corporation)

5C-3 Power Reduction Technique of On-Chip Memory Test
♠Tomonori Sasaki (Renesas Electronics Corporation)

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