Tutorial 1

Sept. 3 Tuesday (9:00 am – 12:30 am), @1204 room

Machine Learning for Reliability of ICs and Systems

Lecturers:  Mehdi Tahoori (Karlsruhe Institute of Technology),

                             Krishnendu Chakrabarty (Duke University)


Tutorial 2

Sept. 3 Tuesday (1:30 pm – 5:00 pm), @1204 room

AI Chip Technologies and Its DFT Methodologies

Lecturers:  Yu Huang (Mentor, A Siemens Business),

                         Rahul Singhal (Mentor, A Siemens Business),

                         Lee Harrison (Mentor, A Siemens Business)


Embedded Tutorial

Sept. 4 Wednesday (2:45 pm – 3:45 pm), @1204 room

Highly Dependable Many-Processor Systems-on-Chip for Cars

Lecturer:  Hans G. Kerkhoff (University of Twente)


 The fast developments in semiconductor processing have made the integration of large numbers of processor cores as well as AMS IPs in Systems-on-Chips possible. However, the dependability of CPSoCs is rapidly decreasing. Especially in demanding automotive safety-critical applications under harsh environments, this life time can be far less than the guaranteed lifetime of the system. A conventional technique to solve this issue can be the careful design of the IPs under worst-case conditions, at the cost of a much larger design time, no reuse options and less performance. A recent approach is the periodic (scan) test of each (digital) IP during life time, via a so-called dependability manager, and subsequently recalibrate IPs or deactivate faulty IPs while activating remaining signal-processing resources. However, this usually results in a significant down-time (boot-up) which is often not allowed. A new very promising method uses IJTAG-compatible embedded instruments (EI) which are monitoring environmental and process conditions as well as aging and performance parameters of IPs. They are on-chip and on-line, providing potentially a vast amount of data with regard to the degrading IPs in SoCs and not interrupting their functionality. By employing data fusion of EIs based on machine learning techniques (on-board neural processor) and subsequent remaining life-time prediction, an IP can be recalibrated or (electronically) disconnected from the system and activate new resources without any down time. The presentation will be illustrated by actual implementations and measurement results.

About the Lecturer:

 Hans G. Kerkhoff received his M.Sc. degree in Telecommuni-cation with honours at the Technical University of Delft in 1977, the Netherlands. In the same year he became staff member of the chair IC-Technology & Electronics at the Faculty of EE, University of Twente in Enschede, the Netherlands.

 Prof. Hans G. Kerkhoff obtained a Ph.D. in Technical Science (micro-electronics) at the University of Twente in 1984. In the same year he was appointed associate professor in Testable Design and Testing (TDT) at the Faculty of EE at the University of Twente. In 1991, he became head of the research group TDT of the MESA+ Research Institute (for Nanotechnology) and headed the MESA Test Centre (MTC). In 1992 he spent his sabbatical year at the test company Advantest in Silicon Valley, USA. From 1995 up to 1999, he worked in addition part-time at the Philips Research Laboratories in the VLSI Design and Test Group at Eindhoven. In 2000, he founded the company TwenTest, specializing in consultancy in the area of testable design and test of dependable mixed-signal microsystems. Currently he is with the Digital Society Institute (DSI), the largest research institute of the University of Twente, heading the CAES-TDT group and responsible for Hardware Dependability of Systems-on-Silicon. He advised 26 Ph.D. students in this research area and has (co-) authored over 330 publications. He is and has been involved in many national (STW, FOM) and European (FP3-FP7, MEDEA, MEDEA+, Catrene, ENIAC, Penta, Horizon 2020) scientific projects.

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