Invited Talk 1 (Wednesday, Sept. 13)

Title: Moore Meets Murphy

Speaker: Erik Jan Marinissen (imec)

Chair: Masayuki Arai (Nihon University)

Abstract

Gordon Moore’s iconic 1965 article unwittingly laid the foundation for a remarkably accurate prediction that has withstood the test of time. His forecast has turned into an industry target, holding immense significance. For decades, downsizing metal and poly pitches effortlessly propelled progress, but now the technical and economical limits of this scaling approach are in sight. Today, the semiconductor industry seeks salvation in the vertical dimension through die stacking, commonly referred to as “chiplet-based design”. However, even these multi-die packages, like all integrated circuits, are susceptible to Murphy’s Law and necessitate rigorous testing for manufacturing defects. Beyond the usual obstacles of test content, accessibility, and cost, chiplet-based ICs present their own unique set of test challenges. This presentation aims to scrutinize these hurdles and explore emerging solutions, if available.

About the Speaker

Erik Jan Marinissen is Scientific Director at imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he holds the position of Visiting Researcher at Eindhoven University of Technology (TU/e) in the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale. He holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992) from TU/e. Marinissen has an extensive publication record, co-authoring more than 285 journal and conference papers and being involved in the invention of eighteen US/EP patent families.

Marinissen has played significant roles in standardization and academic initiatives. He served as Editor-in-Chief of IEEE Std 1500™-2005, which focuses on embedded core test access, and initiated and chaired IEEE Std 1838™-2019, addressing 3D test access. Additionally, he founded workshops such as ‘Diagnostic Services in Network-on-Chips’, ‘3D Integration Workshop’, and the IEEE ‘International Workshop on Testing Three-Dimensional Stacked ICs’. Marinissen has also taken on key positions as Program Chair and General Chair for several conferences, including DDECS, ETS, 3D-TEST, 3DC-TEST, DATE, ETW, DSNOC, and 3DIW. Moreover, he serves on various conference committees, contributing to events such as ATS, DATE, ETS, ITC, ITC-Asia, and VTS. Marinissen serves on the editorial boards of IEEE ‘Design & Test’ and Springer’s ‘Journal of Electronic Testing: Theory and Applications’. Throughout his career, Marinissen has received numerous prestigious awards, including Best Paper Awards at various conferences and symposiums. Both in 2008 and 2010, he won the Most Significant Paper Awards at the IEEE International Test Conference (ITC). In 2017, he received both the National Instruments’ Engineering Impact Award and the IEEE Standards Association’s Emerging Technology Award. At ITC 2021, Marinissen received the TTTC Bob Madge Innovation Award. Notably, he was recognized as the most-cited author of ITC papers from 1995 to 2019 on ITC’s 50th anniversary in 2019. He is also included in the list of “Top-2% Scientists World-Wide in All Disciplines” published by Elsevier and Stanford University. Marinissen is a Fellow of IEEE, a Distinguished Contributor Charter Member, and a Golden Core Member of IEEE Computer Society. He served as an elected member of the IEEE Computer Society’s Board of Governors from 2019 to 2021. Marinissen has also shared his expertise through tutorials and in-house company courses on Core-Based SOC Test, 3D-SIC Test, and Improving ATPG Test Quality at various international conferences and events.

As an educator, Marinissen has supervised over 49 international MSc and PhD students, fostering their growth and development in the field. Notably, Dan Adolfsson, one of his MSc students from Linköping Universitet in Sweden, received the “Sveriges Ingenjörer ‘Lilla Polhempriset’” in 2007 for his outstanding MSc graduation project supervised by Marinissen at NXP Semiconductors. Furthermore, Lizhou Wu, a PhD student at TU Delft in the Netherlands, was honored with the TTTC Edward J. McCluskey Best Doctoral Thesis Award in Test at ITC in 2021 for his exceptional PhD thesis titled “Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions”, which received a “cum laude” distinction.

Invited Talk 2 (Thursday, Sept. 14)

Title: Test Industry Challenges and Solutions as Observed by the Leading Physical Implementation Solution Provider

Speaker: Janet Olson (Cadence Design Systems, Inc.)

Chair: Satoshi Komatsu (Tokyo Denki University)

Abstract

Test is a mission critical aspect of the design process, but design functionality/verification consumes the significant majority of engineering focus, with test often retrofitted late in the design cycle. The era of point-tools is over, what’s needed is deep collaboration across the flow from state-of-the-art design IP, verification, physical design, and packaging. New solutions must manage test structures from multiple sources and meet coverage, test time, and PPA (power, performance, area) goals without introducing design closure iterations. This presentation offers a new way forward, borne from Cadence’s unique perspective gained from experience working with global semiconductor suppliers engineering test into some of the world’s most complicated designs.

About the Speaker

Janet Olson is Vice President Research and Development for Front-End Design at Cadence Design Systems. Janet is responsible for Modus, Cadence’s IC test solution, high level synthesis (Stratus) and constraint verification (Litmus). Janet has a master’s degree in Electrical Engineering from Stanford and a bachelor’s degree from CMU and holds 7 US patents. Janet has been recognized with the 2017 Marie R. Pistilli Electronic Design Award and the 2016 YWCA Tribute to Women award.