Tutorial 1 (9:00 am – 12:00 pm on Tuesday, Sept. 12)
Title: Scalable hierarchical DFT technologies for AI, SOC and multi-die
Lecturers: Lee Harrison and Wu Yang (Siemens EDA)
Abstract
In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next, we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. Similarly, we will the discussion on DFT for typical HPC SOC designs. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry, the new challenges added for the DFT community and the solutions. Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities.
Intended audience
Researchers and engineers interested in Hierarchical, tile based and multi-die DFT technologies for AI chip and large SoC designs.
Keywords
Machine Learning, Neural Networks, Deep Learning, Artificial Intelligence (AI), AI Chips, DFT, ATPG, 3D Testing, tiling, IEEE 1687, IEEE1838, Diagnosis, Yield Learning, chiplet, multi-die
Duration
3hrs with 10mins of break
About the Lecturers
Lee Harrison, is Tessent Product Marketing Director for safety and security, at Siemens EDA. He has over 20 years of industry experience with Siemens Tessent test, safety and security products, with a focus on automotive, Lee is working to ensure that current and future test, safety, security and analytics requirements of Siemens’s automotive customers are understood and met. Lee received his BEng in Micro Electronic Engineering from Brunel University London in 1996.
Wu Yang is the Director of marketing at Siemens EDA. With more than 24 years of experiences in DFT, 3D IC, silicon learning and testing, Mr. Yang has been a frequent speaker at many conferences and a regular contributor to papers and articles. He delivered multiple tutorials at ITC, ATS, ETS and VTS. Mr. Yang received a MS degree in electrical engineering from Portland State University.
Tutorial 2 (1:00 pm – 4:00 pm on Tuesday, Sept. 12)
Title: Silicon Lifecycle Management: Trends, Challenges and Solutions
Lecturer: Yervant Zorian (Synopsys, Inc.)
Abstract
Recent advances in automotive SOCs, artificial intelligence accelerators, and high-performance computing engines in data centers have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. This tutorial will present today’s trends and discuss on the resiliency challenges for such emerging SOCs. It will then focus on optimizing the SOC health using advanced solutions typically utilized for managing the different silicon lifecycle stages: from silicon debug in early bring up stage to shorten the time-to-volume; to self-test and repair during volume production stage, in order to improve quality and yield; to power-on self-test in the field stage to address aging challenges; to periodic checking in-system to improve functional safety; and finally to fault tolerance and error correction during mission mode to address a range of transient errors. All of the above optimizations are materialized by on-chip and/or off-chip data analytics.
About the Lecturer
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.