Sept. 13 (Wednesday) 1:00 pm – 2:15 pm
Suffix ‘s’: short presentation
Regular 1A @Int’l Conf. Hall: Hardware Security
Chair: Jiun-Lang Huang (National Taiwan University)
[1A-1] A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation
Kentaroh Katoh (Fukuoka University), Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi (Gunma University), Keno Sato, Takashi Ishida, Toshiyuki Okamoto and Tamotsu Ichikawa (ROHM Semiconductor)
[1A-2] Hunting for Hardware Trojan in Gate Netlist: A Stacking Ensemble Learning Perspective
Liang Hong, Ge Zhu (Northwestern Polytechnical University), Jing Zhou (Beijing Microelectronics Technology Institute), Xuefei Li, Ziyi Chen and Wei Hu (Northwestern Polytechnical University)
[1A-3s] Optimizing Post-Silicon Validation for FPGA Serial Configuration using an Automation Framework and Timing Characterization Verification
Mohd Amiruddin Zainol, Khamron Sompon and Gua Bin Ng (Intel Corporation)
Special 1B @Room 501: 3D Chiplet Test Session 1
Chair: Xiaoqing Wen (Kyushu Institute of Technology)
[1B-1] On-Chip Timing Circuits for Finding Who’s Accountable When a 3D Chiplet IC Fails
Shi-Yu Huang (National Tsing Hua University)
[1B-2] Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency
Po-Yao Chuang (imec)
Special 1C @Room 601: Siemens Session (Silicon Lifecycle Management)
Chair: Wu Yang (Siemens EDA)
[1C-1] Silent Data Corruption (SDC) Failures — What Do We Know about the Root Causes?
Phil Nigh (Broadcom, Inc.)
[1C-2] Production Test Impacts of Chiplet Integration within a 3DIC
Vineet Pancholi (Amkor Technology, Inc.)
[1C-3] Functional Monitoring of Complex Chips
Lee Harrison (Siemens EDA)
[1C-4] High Protocol Scan with System Level Test
John Jackson (Teradyne, Inc.)
Sept. 13 (Wednesday) 2:45 pm – 4:00 pm
Suffix ‘s’: short presentation
Regular 2A @Int’l Conf. Hall: Defect Analysis
Chair: Andre Ivanov (The University of British Columbia)
[2A-1] Toward Improvement and Evaluation of Reconstruction Capability of CapsNet-Based Wafer Map Defect Pattern Classifier
Yuki Yamanaka (Tokyo Metropolitan University), Masayuki Arai (Nihon University), Yoshikazu Nagamura and Satoshi Fukumoto (Tokyo Metropolitan University)
[2A-2] Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS
Hao-Chiao Hong, Chien-Hung Chen and Yu-Wun Chen (National Yang Ming Chiao Tung University)
[2A-3s] Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test
Chen-Lin Tsai and Shi-Yu Huang (National Tsing Hua University)
Special 2B @Room 501: 3D Chiplet Test Session 2
Chair: Senling Wang (Ehime University)
[2B-1] Emerging Trends, Challenges and Solutions for Probing Next Generation Advanced Packaging Devices
Cameron Harker (FormFactor Inc.)
[2B-2] On the application of boundary scan design with embedded time-to-digital converter to 3D stacked IC
Hiroyuki Yotsuyanagi (Tokushima University)
[2B-3] TSV Bonding Evaluation Technology in 3D-IC by Improved Analog Boundary Scan
Shuichi Kameyama (Ehime University)
Special 2C @Room 601: Industry Session 1
Chair: Jun Matsushima (Renesas Electronics)
[2C-1] Development and Verification of Wet Testing Platform for BioMEMS Chips
Poting Lai (King Yuan Electronics Co., Ltd)
[2C-2] On Evaluation of Technique for Aging Detection and Prediction with Accelerated Life Test
Takaaki Kato (PRIVATECH Inc.)
[2C-3] Innovus Test Points – Enabling the Next Leap in Coverage and Test Pattern Reduction
Janet Olson (Cadence Design Systems, Inc.)
Sept. 14 (Thursday) 1:00 pm – 2:15 pm
Suffix ‘s’: short presentation
Regular 3A @Int’l Conf. Hall: Processor/Software Testing
Chair: Jin-Fu Li (National Central University)
[3A-1] BDD-Based Self-Test Program Generation for Processor Cores
Hao Chen, Chi-Jhe Li, Hung-Lin Chen and Jiun-Lang Huang (National Taiwan University)
[3A-2s] Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors
Bin Zhang, Ye Cai (ShenZhen University), Zhiheng He (Beijing Institute of open source chip), Sen Liang (Chinese Academy of Sciences) and Wei He (PengCheng Laboratory)
[3A-3s] Software Defect Detection Based on Feature Fusion and Alias Analysis
Xuejian Li and Zhengguang Zhu (Anhui University)
Regular 3B @Room 501: Fault Tolerant Latch
Chair: Tong-Yu Hsieh (National Sun Yat-sen University)
[3B-1] A Low Overhead and Double-Node-Upset Self-Recoverable Latch
Aibin Yan, Fan Xia (Anhui University), Tianming Ni (Anhui Polytechnic University), Jie Cui (Anhui University), Zhengfeng Huang (Hefei University of Technology), Patrick Girard (University of Montpellier) and Xiaoqing Wen (Kyushu Institute of Technology)
[3B-2] Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness
Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui (Anhui University), Zhengfeng Huang (Hefei University of Technology), Patrick Girard (University of Montpellier) and Xiaoqing Wen (Kyushu Institute of Technology)
[3B-3] Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications
Anwesh Kumar Samal, Sandeep Kumar and Atin Mukherjee (National Institute of Technology Rourkela)
Special 3C @Room 601: Industry Session 2
Chair: Kazumi Hatayama (EVALUTO)
[3C-1] Strategies to Reduce Memory Test Time during Power-On Self-Test for Automotive Products
Yudai Kawano (Renesas Electronics Corporation)
[3C-2] mm-Wave Connection Technology for Semiconductor Test
Hiroyuki Yamakoshi (S.E.R. Corporation)
[3C-3] High Accuracy Defect Identification Method by using TDR with Femto-second Laser Technology
Makoto Shinohara (ADVANTEST CORPORATION)
Sept. 14 (Thursday) 2:45 pm – 4:00 pm
Suffix ‘s’: short presentation
Regular 4A @Int’l Conf. Hall: Testing and Verification
Chair: Yoshinobu Higami (Ehime University)
[4A-1] On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults
Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume (Tokushima University)
[4A-2s] Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique
Ayano Takaya and Michihiro Shintani (Kyoto Institute of Technology)
Regular 4B @Room 501: Memory
Chair: Hao-Chiao Hong (National Yang Ming Chiao Tung University)
[4B-1] Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory
Shyue-Kung Lu and Xin Dong (National Taiwan University of Science and Technology)
[4B-2] Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications
Aibin Yan, Jing Xiang (Anhui University), Zhengfeng Huang (Hefei University of Technology), Tianming Ni (Anhui Polytechnic University), Jie Cui (Anhui University), Patrick Girard (University of Montpellier) and Xiaoqing Wen (Kyushu Institute of Technology)
[4B-3] Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs
Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li (National Central University), Yun-Ting Chuan and Shih-Hsu Huang (Chung Yuan Christian University)
Regular 4C @Room 601: Jitter and Error Mitigation
Chair: Haruo Kobayashi (Gunma University)
[4C-1] Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test
David Keezer (Georgia Institute of Technology), Dany Minier (Boreas Technologies) and Hongjie Li (Shenzhen Research Institute Tianjin University)
[4C-2s] Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration
Yi-Hsuan Lee, Wei-Hao Chen and Shi-Yu Huang (NTHU)
[4C-3s] Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4
Wei-Ji Chao and Tong-Yu Hsieh (National Sun Yat-sen University)