Special 1B: 3D Chiplet Test Session 1
[1B-1] On-Chip Timing Circuits for Finding Who’s Accountable When a 3D Chiplet IC Fails
Shi-Yu Huang (National Tsing Hua University)
When a 3D Chiplet IC fails, finding the root cause(s) is especially important. On one hand, the chip integrator can use the information to track the robustness and yield of each constituent die. On the other hand, it can help settle the disputes of which die provider(s) should be held accountable for the failure. In this talk, we highlight some easy-to-neglect issues that may become the bottlenecks of this root-cause process. For example, the failure could be caused by small delay faults that degrade the performance of some functional dice or macros. Also, it could be due to parametric defects in the logistic networks such as the clock network and the power network, or the die-to-die interconnects. For dealing with these atypical types of failures, we ponder what extra timing circuits and test schemes could be useful when added to the traditional Design-for-Testability technologies using scan architecture, core-based test infrastructure, and built-in self-test.
[1B-2] Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency
Po-Yao Chuang (imec)
Chiplet-based multi-die packages (2.5D- and 3D-ICs) implement micro-bumps for inter-die interconnects, which are subject to manufacturing defects. Traditional interconnect automatic test pattern generation (I-ATPG) methods, like True/Complement Algorithm, focus only on hard open and short defects with 2×⌈log_2 (k)⌉ test patterns for k interconnects. The E^2 ITEST algorithm proposed in this paper improves test effectiveness by covering hard and weak variants of open and short defects. It supports fault diagnosis, prevents aliasing, and requires only 8×⌈log_2 (4)⌉=16 test patterns, thus decoupling it from the expected-large k growth.
Special 1C: Siemens Session (Silicon Lifecycle Management)
[1C-1] Silent Data Corruption (SDC) Failures — What Do We Know about the Root Causes?
Phil Nigh (Broadcom, Inc.)
SDC failures have gotten a lot of discussion in the industry due to concerns about errors in Data Centers that are not detected. But there has not been much information about the root cause of SDC failures: reliability latent failures? wear out? soft/transient errors? marginal defects? We’ve been characterizing and diagnosing SDC failures for the last two years (ATE characterization). In this talk we’ll summarize what we’ve learned.
[1C-2] Production Test Impacts of Chiplet Integration within a 3DIC
Vineet Pancholi (Amkor Technology, Inc.)
Chiplet-based design adds new issues to the testing process. Tests must now cover individual chiplets, the interconnections among them, and the entire package. Depending on the design complexity, testing could significantly increase time-to-market. How can developers keep such effects at a tolerable and affordable level? Are there any design for test (DFT) methods available, which when included in the architecture will help with test coverage and yet simplify production testing? EDA (Electronic Design Automation) companies and IEEE forums have significantly contributed and continue to contribute towards the large variety of 3DICs under development. Automation must be stressed, and new techniques such as agent-based monitoring must be evaluated. Test considerations must play a key role in heterogenous integration and package development. Only a thorough integration of test with the entire development process will do the job. Due to higher levels of integration at the package, manufacturing test flows must be altered for most optimal test coverage. System Level Test (SLT) will continue to play a vital role in Manufacturing Test Flows. Content re-distribution in each test step may be necessary.
[1C-3] Functional Monitoring of Complex Chips
Lee Harrison (Siemens EDA)
Functional Monitors (Tessent Embedded Analytics) provides a holistic, system-level view of the complex behaviors within today’s SoCs. The IP and software help engineers to implement safety and cybersecurity functions in hardware; and to more quickly and cost effectively debug and optimize hardware and software in the lab and in the field.
[1C-4] High Protocol Scan with System Level Test
John Jackson (Teradyne Inc.)
Testing challenges continue to increase as semiconductor geometries become smaller and packaging complexity increases. System level test (SLT) is becoming more common as a method to meet these challenges. In parallel with the rise of SLT, testing across the life cycle of parts is also becoming more common. With these changes, it is increasingly useful to run scan tests at SLT and in the field-a low-cost method for running high-yield patterns that might seem marginally cost-effective to run at final test. Running high-protocol scan testing-serial scan using high-level protocols such as USB or PCIe delivers better diagnostic capabilities in the field. The use of standard protocols allows the device under test’s (DUT)scan features to be easily accessible for SLT and in the field, given that the necessary hardware can be designed to be highly parallel (SLT) or portable (field). John will discuss high protocol scan testing, and methods for meeting the challenges described above.
Special 2B: 3D Chiplet Test Session 2
[2B-1] Emerging Trends, Challenges and Solutions for Probing Next Generation Advanced Packaging Devices
Cameron Harker (FormFactor Inc.)
As the semiconductor industry continues into the post Moore’s Law era, Advanced Packaging continues to emerge as an enabling technology for next generation devices that require increased performance, computing power and bandwidth all while driving lower costs. 2.5D and 3D IC packaging technology is being utilized for ever increasing applications. These increased performance requirements are driving new and ever-increasing test challenges in order to insure device performance and yield with commercially viable costs. Test strategies and solutions are evolving in order to support these requirements. This presentation will review the current trends in advance packaging options, particularly 2D and 3D IC technology along with the test requirements from a probe card perspective and probe card solutions to meet the current and next generation device testing.
[2B-2] On the application of boundary scan design with embedded time-to-digital converter to 3D stacked IC
Hiroyuki Yotsuyanagi (Tokushima University)
A defective TSV may cause a small delay that is hard to be detected using logic testing. We have proposed a boundary scan design with an embedded time-to-digital converter circuit to detect delay faults in interconnects. The proposed design was implemented in a prototype 3D IC stacked by TSVs with different diameters. The measurement results show that the proposed delay testable circuit can detect both logic errors that occurred in TSVs with smaller than standard diameters and significant signal delay through a TSV with no logic error.
[2B-3] TSV Bonding Evaluation Technology in 3D-IC by Improved Analog Boundary Scan
Shuichi Kameyama (Ehime University)
Hybrid bonding is emerging in addition to conventional micro-bump solder bonding to achieve even higher TSV densities. With the miniaturization of junctions, advanced technological development is required to assure the quality and reliability of interconnections, so the technology to evaluate it is important. By improving the Analog Boundary-Scan (IEEE 1149.4), we have developed a technology that can measure and evaluate individual junction low resistance (<1Ω) in a large number (>10,000) and fine pitch (<40um pitch) TSVs with high accuracy (<10mΩ) and in a short time (<1 hour/10,000TSV). These measurements were not possible with the conventional daisy chain method or 4-wire method. This technology can also be linked with temperature cycle and vibration tests, enabling efficient TSV bonding evaluation.
Special 2C: Industry Session 1
[2C-1] Development and Verification of Wet Testing Platform for BioMEMS Chips
Poting Lai (King Yuan Electronics Co., Ltd)
According to the yole2022 report, the production value of silicon-based biomedical chips is expected to reach US$900 million by 2027, among which BioMEMS is a rapidly developing field in Biomedical chips. After the outbreak of COVID-19, many medical institutions found that traditional PCR testing was too slow, so many companies have invested in the development of new types of BioMEMS. MEMS technology can reduce the size of Biomedical chips and integrate microfluidic. Due to the microstructure on BioMEMS, the testing requires only a small amount of sample, reagent, and testing time to obtain results. On the other hand, even with the strong performance of BioMEMS, due to the lack of mature mass production testing technologies, the low coverage rate of mass production testing causes the BioMEMS production capacity unable to increase. In this study, this study developed a wet testing platform basis of BioMEMS chips and obtained stable and highly reproducible measurement results after verification. Since BioMEMS chips require wet testing to verify product yield, and during wet testing, the solution to be tested needs to be dropped onto the sensing area (array) of the chip test key, and electrical testing can only be performed after probing on pad of test key. In addition, due to the restriction of the structure and size of the BioMEMS chip, the volume of the solution to be tested must be controlled within a micro volume of 1 μl. Based on the above situations, this study developed the wet testing platform according to the droplet testing method in the past. The wet testing platform integrates and optimizes the probe station, semiconductor analyzer, and microfluidic control system. Besides, the testing method also verified the influencing factors such as solution concentration, different solutions, solution cleaning method, testing time, and needle force, and used the experimental results to improve the testing process. This testing platform and process were also verified with the BioMEMS chips, and the measurement data of electrical properties not only showed the accuracy but also reproducibility. In summary, the developed wet testing platform can provide reliable electrical measurement capability and has the potential to be developed into a semi-automatic and fully automatic testing platform. The technology is expected to be applied in the field of contract manufacturing testing in the future.
[2C-2] On Evaluation of Technique for Aging Detection and Prediction with Accelerated Life Test
Takaaki Kato (PRIVATECH Inc.)
An on-chip path delay measurement in a field is effective for aging detection and prediction, where the aging depends on an operating environment. We have developed a technique for aging detection and prediction in a field using the delay measurement and an on-chip temperature and voltage sensor to eliminate environmental effects. This presentation shows that evaluations of TEG chips equipped with the delay measurement technique and the sensors in 28nm and 40nm CMOS technology. The 40nm chips are evaluated with accelerated life test. Then, it was confirmed that the aging can be measured towards practical application.
[2C-3] Innovus Test Points – Enabling the Next Leap in Coverage and Test Pattern Reduction
Janet Olson (Cadence Design Systems, Inc.)
Test Points were introduced over three decades ago, with the goal of increasing controllability/observability and reducing the number of test patterns. Despite the maturity of the solution, adoption has been muted due to the adverse impact that Test Points have on design closure. Generally, Test Points create timing, power and congestion issues making it more difficult to close PPA, resulting in logical to physical design iteration. The solution requires deep integration of Test Point insertion within the Innovus placer. The solution can be extended with Cadence Cerebrus AI/ML for further gains in coverage and test pattern reduction. This presentation discusses Cadence’s unique solution, that enables design teams to use Test Points to achieve the promise of Test Points—increased coverage, with fewer test patterns, and minimal adverse impact on design PPA and closure.
Special 3C: Industry Session 2
[3C-1] Strategies to Reduce Memory Test Time during Power-On Self-Test for Automotive Products
Yudai Kawano (Renesas Electronics Corporation)
Power-on Self-test (POST) is a functional safety feature of automotive systems, which tests memory and logic within a limited time at power-on. As the memory test time and power consumption of POST have been increasing due to the higher memory capacity and speed, measures are needed to suppress them. It is also required to notify the status of individual memories that have detected failures. We introduce a new method to reduce POST execution time in our products, such as Error Check and Correction (ECC) availability check using memory BIST results and CPU core test considering power consumption as well as the usual memory test.
[3C-2] mm-Wave Connection Technology for Semiconductor Test
Hiroyuki Yamakoshi (S.E.R. Corporation)
This presentation introduces various spring probe interconnect applications with validation data for highly demanding and diversified semiconductor test. For recent RF and high-speed devices, the specialized test socket geometry and measurement techniques are needed to meet the test requirements for those devices. The presentation is included several test socket applications with unique technology and test data for market requirements as follows.
– Super Short Probe socket for Antenna in Package (AiP) and high frequency passive devices, i.e. RF filter.
– KTC multi-channel coaxial connector for RF device evaluation and quantum computing
– Differential 112G bps PAM4 interface.
– Multi-impedance solution for multi-function SoC devices.
[3C-3] High Accuracy Defect Identification Method by using TDR with Femto-second Laser Technology
Makoto Shinohara (ADVANTEST CORPORATION)
A non-destructive defect analysis method for detecting defects in semiconductor device packages in high accuracy has been developed. It utilizes Time Domain Reflectometry (TDR) with a femto-second laser-generated electrical pulse. Our TDR system can identify defects in signal propagation lines with high resolution less than 5 um. And the system successfully locates open defects in bonding segments of complex and fine structure as 2.5D/3D IC Package without any package destruction. This innovative approach offers precise defect identification and location, enhancing semiconductor manufacturing quality and reliability.